The present invention relates to a delay device having a time constant delay circuit comprising a capacitor and a resistor.
FIG. 4 is an example of a conventional delay device.. In FIG. 4, a reference numeral 2 designates a delay circuit comprising a capacitor 203 and a resistor 202 in which an electric charge in the capacitor 203 is discharged through the resistor 202 to thereby output a delay signal e. A reference voltange circuit 5 is connected to the collector of a transistor 3. When the level of an input signal a becomes "0", the transistor 3 becomes non-conductive state to open the ground circuit, whereby the capacitor 203 is charged by the reference voltage circuit 5 through a diode 4. Namely, when the input signal a is at a level of "0", the transistor 3 becomes non-conductive, and the capacitor 203 is quickly charged to a predetermined level by the reference voltage circuit 5 through the diode 4. When the level of the input signal a is changed to level of "1", the transistor 3 is turned on so that the reference voltage circuit 5 is grounded. Then, a charging circuit to the capacitor 203 is opened, and at the same time, the capacitor 203 starts discharging through the resistor 202. A discharging time is determined by the product of the capacitance c of the capacitor 203 and the resistance R of the resistor 202, i.e. a time constant of CR. Thus, a signal indicated by a in FIG. 3 is obtainable as a delay signal e.
In the conventional CR delay device having the construction as above-mentioned, when a long delay time is to be obtained, it is necessary to increase the CR constant. When the CR delay device is installed in a hybrid IC, it is difficult to use a resistor having a large resistance because of a problem of leakage. Further, a capacitor having a large capacitance, hence having a relatively large outer configuration occupies a larger area on the base substrate for a hybrid IC. On the other hand, there is a demand to increase the packing density in the field of hybrid IC. A delay device having a long delay time constructed by the conventional technique reduces the efficiency in such hybrid IC.